Bumping is a wafer level advanced packaging technology. The bumps are typically formed upon under bump metallization (UBM) which is electroplated on the die pads openings.
CP (Chip Probing) is to test the electrical and functional performance of the chips on wafer level by using Automatic Test Equipment(ATE) and probe cards.
SJSemi’s WLCSP solution providing the best service to global top chip design houses and end product customers, can meet different product application and technologies.
SJSemi's novel, patented technology enables 3D integration of the active and passives devices. This 3D integration leads to lower power delivery loss and higher performance per watt. Its key enabling technologies comprise of ultra-high Cu vertical interconnect, multi-layer double sided fine pitch RDLs, wafer-level multi-layer precise aligned antennas, flip-chip and SMT.
SmartPoser™ technology platform derives novel 3D heterogeneous integration of active and passive devices to achieve high bandwidth, high speed and low power consumption for higher system level performance.
Realized high density, high integrated and ultra-thin 3D chip integration, SmartPoser-HD is a wafer level system package technology derived from SmartPoser™ technology platform, which has high density RDL and vertical interconnect to realize high density 3D integration, and to provide high performance package solutions for various applications, such as mobile, HPC and AI.
The world’s first 5G mm-Wave ultra-wideband dual polarization AiP package technology, SmartAiP is a wafer level antenna in package technology derived from SmartPoser™ technology platform. The SmartAiP realizes the dream characteristics for the 5G mm-Wave. Its ultra-wideband works from 24GHz to 43 GHz. Besides, it has handset friendly form factor with less than 1 mm thickness, and still roomy for RFFE module integration and good at heat dissipation.
SJSemi is the first Middle-End-Of-Line (MEOL) pure play foundry equipped with Front-End-Of-Line (FEOL) manufacturing and quality system, serving global customers.
SJSemi devotes to offer first-class Middle-End-Of-Line (MEOL) manufacturing and testing services and develops to provide the advanced 3D Multi-Die Integration technology and solutions.
JIANGYIN, China, March 16, 2022 -- SJ Semiconductor Co. (SJSemi), a leading MEOL (Middle-End-Of-Line) foundry specializing on advanced Bumping and 3D Multi-Die Integration technology, is pleased to announce that its Series C financing of $300 million has been fully closed